The machine protection system guarantees the safe operation of the HIAF (High Intensity heavy-ion Accelerator Facility) in different operating modes and also prevents damage to the online equipment in the event of a failure. Beam current data such as beam current position and phase is an important basis for analysing and diagnosing accelerator faults. In this paper, the authors designed the beam position and phase interlock monitoring system. The system is based on circular buffer and AXI4 protocol to realize the interaction of interlock data and locking of interlock status. At the same time, the system uses memory mapping to save the interlock beam data. Laboratory tests show that the system could save the beam position, beam phase, SUM signals and amplitude of sensed signal per probe path during interlocking before and after 8ms and latch the interlock status of 25 channels. The system was deployed at the CAFe-LINAC gas pedal in March 2024 to complete online measurements.

The High Intensity Heavy-ion Accelerator Facility (HIAF), currently under construction, is a complex machine that couples a Continuous Wave (CW) superconducting ion Linear accelerator (iLinac) with a high-energy synchrotron to produce various stable and radioactive intense beams with high energies. The machine has a versatile operation mode which requires a high flexibility and reliability to the Machine Protection System (MPS). A customized and robust MPS is designed and developed to give the readiness of the machine for operation, to mitigate and analyze faults related to the relative damage potential. To get a high speed and have a high level of reliability, all interlock signal processing is processed on radiation-tolerant Field-Programmable Gate Arrays (FPGA) with triple or dual redundancy, as well as with a fail-safe design. By implementing a multiprocessing platform system-on-chip FPGA, the HIAF MPS can be tightly integrated with other systems to maximize availability pinpoint failures for operations, and give the postmortem analysis. This paper will describe the architecture of the interlocks linking the protection systems, the strategies to manage the complexity, the detailed components, and the interlock logic of the customized HIAF MPS, as well as the test and verification of the prototype.

Insertion devices (IDs) are currently being installed at the SIRIUS storage ring to provide photon beams for upcoming high-brilliance beamlines. A fast orbit distortion detection system is imperative to safeguard critical vacuum chambers located near the straight sections of the IDs. In November 2023, an in-house Delta undulator was successfully installed, and a fast orbit interlock protection system has been in place, utilizing BPMs and the timing system's infrastructure. A dedicated position and angle calculation is implemented in FPGA and operates at a 6 kHz rate in the BPM processing electronics. A timing receiver board at the BPM uTCA crate acts as a bridge between orbit distortion detection and the timing system’s event generator (EVG), which sends an interlock signal to the LLRF controller. The main purposes of this work are to provide details about a new full-duplex timing network implementation, to discuss the main requirements of the orbit interlock, and to present measured performance results. Additionally, in pursuit of enhancing system reliability, post-mortem analysis and ongoing implementation proposals will also be presented.